1. Field of the Invention
The present invention relates to a technique for stabilizing a common voltage supplied to a liquid crystal display panel of a liquid crystal display (LCD) device and, more particularly, to a circuit for stabilizing a common voltage of an LCD capable of minimizing generation of a panel blur (mura) resulting from a common voltage becoming unstable due to a capacitance component within a panel.
2. Description of the Related Art
In general, because the LCD has characteristics that it is light and thin and driven at low power consumption, its use has extended to office automation devices or an audio/video device. The LCD displays a desired image on its screen by controlling transmittance of a light according to image signals applied to a plurality of control switches arranged in a matrix form.
FIG. 1 is a schematic block diagram of an LCD according to a related art. As illustrated, the related art LCD includes a liquid crystal display panel 13 in which a plurality of data lines DL and a plurality of gate lines GL cross and thin film transistors (TFTs) for driving liquid crystal cells are formed at crossing points of the data lines and the gate lines; a data driving unit 11 for providing data to the data lines DL; a gate driving unit 12 for providing scan pulses to the gate lines GL; and a timing controller 14 for outputting various control signals for controlling the data driving unit 11 and the gate driving unit 12 and outputting video data (R, G and B).
The operation of the LCD will now be described with reference to FIGS. 2 and 3.
The liquid crystal display panel 13 is constructed such that liquid crystal is provided between two glass substrates, and the data lines DL and the gate lines GL cross on the lower glass substrate. TFTs formed at the crossing points of the data lines DL and the gate lines GLS provide data received from the data lines DL to liquid crystal cells in response to scan pulses from the gate lines GL. For this purpose the gate terminal of each TFT is connected with a respective gate line GL and the source terminal of each TFT is connected with a respective data line DL. A drain terminal of each TFT is connected with a respective pixel electrode of each liquid crystal cell Clc. A storage capacitor Cst for sustaining a voltage of liquid crystal cells is formed on the lower glass substrate of the liquid crystal display panel 13.
The timing controller 14 receives digital video data (RGB), a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync and a clock signal CLK; generates a gate control signal GDC for controlling the gate driving unit 12; and generates various data control signals DDC for controlling the data driving unit 11. In addition, the timing controller 14 serves to transfer data provided from an external system to the data driving unit 11.
The gate driving unit 12 includes a shift register for sequentially generating scan pulses in response to the gate control signal GDC from the timing controller 14, a level shifter for shifting a swing width of the scan pulse into a level suitable for driving the liquid crystal cell Clc, and an output buffer, etc. The gate driving unit 12 provides the scan pulses to the gate lines GL to turn on the TFTs connected with the gate lines GL, and accordingly, to select liquid crystal cells Clc of one horizontal line to which a pixel voltage, namely, an analog gamma compensation voltage, is to be supplied. Data generated from the data driving unit 11 are provided to the liquid crystal cells Clc of the selected horizontal line by the scan pulse.
The data driving unit 11 provides data to the data lines DL in response to a data drive control signal DDC provided from the timing controller 14. The data driving unit 11 samples the digital data RGB from the timing controller 14, latches it, and then, converts it into an analog gamma voltage.
For reference, in the above description, the data driving unit 11 and the gate driving unit 12 are separately installed on the liquid crystal display panel 13. In this respect, recently, the data driving unit 11 and the gate driving unit 12 may be integrated into a plurality of ICs and mounted on a TCP (Tape Carrier Package) so as to be connected to the liquid crystal splay panel 33 in a TAP (Table Automated Bonding) method or mounted on the liquid crystal display panel 33 in a COG (Chip On Glass) method.
FIG. 2 illustrates a circuit for generating a common voltage Vcom provided to each liquid crystal cell Clc on the liquid crystal display panel 13. As shown, a resistor R21, a variable resistor VR21 and a resistor R22 are connected in series between a power source terminal Vdd and a ground terminal GND and the common voltage Vcom is outputted from a contact between the resistor R21 and the variable resistor VR21.
Accordingly, the common voltage Vcom is outputted as a level of a DC voltage divided by the resistor R21, the variable VR21 and the resistor R22, and the level can be adjusted by the variable resistor VR21.
The common voltage Vcom may be provided as a DC voltage in a stable form, namely, a DC voltage of a pre-set level, in any situation. However, coupling occurs due to a capacitance component on the liquid crystal display panel 13. As illustrated in FIG. 3, the common voltage Vcom becomes unstable in a blanking interval during which there is no data because of the capacitance component, such as the liquid crystal cell Clc, the storage capacitor Cst, or a Cgs.
Thus, a panel blur phenomenon or a horizontal crosstalk (C/T), etc. is generated to degrade picture quality.